The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occur in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with ultra-low-k (ULK) dielectrics flip chip package are used and are facing significant reliability challenges. The ultra-low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines.  With low modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poorer adhesion of ultra-low-k material, when it is compared to the common dielectric materials, it becomes a major concern to analyze thermomechanical failures. From our past study, it has been concluded that solder joint reliability (SJR) of the small package depends on the copper content in the printed circuit boards (PCB). Also, the wire bond large PBGA packages are a cost-effective package with a substantial number of solder balls. The substrate and PCB have its impact on the solder ball, the mismatch in CTE of different components cause solder failure. In this paper, critical attention has been given to the copper content present in the PCB of different thicknesses and how PCB thickness is related to SJR. The structure of package plays a vital role in deciding reliability of package, as the different structure can shift stress point or distribute stresses to one or more components. The substrate or PCB stack-up or composition can strongly affect the package life. Many parameters need to be studied and package to substrate ratio is one of its which is discussed in this work. Material characterization of PCB with different thickness has been done. Thermal Mechanical Analyzer (TMA) is leveraged to measure temperature-dependent CTE, Dynamic Mechanical Analyzer (DMA) and Universal testing machine are used for measuring Elastic modulus and Poisson’s ratio. Further, a package assembly for the PCB of different thickness has been a model using ANSYS Workbench 18.0.
- Electronic and Photonic Packaging Division
Reliability Analysis of Ultra-Low-K Large-Die Package and Wire Bond Chip Package on Varying Structural Parameter Under Thermal Loading
- Views Icon Views
- Share Icon Share
- Search Site
Rahangdale, U, Rajmane, P, Misrak, A, & Agonafer, D. "Reliability Analysis of Ultra-Low-K Large-Die Package and Wire Bond Chip Package on Varying Structural Parameter Under Thermal Loading." Proceedings of the ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. San Francisco, California, USA. August 29–September 1, 2017. V001T01A020. ASME. https://doi.org/10.1115/IPACK2017-74279
Download citation file: